This invention relates to programmable logic device (“PLD”) integrated circuits, and more particularly to clock circuitry for use on PLDs.
PLDs typically have clock signal input pins that are located so as to facilitate distribution of clock signals from those pins throughout the PLD in a relatively low-skew way. (Skew is different amounts of delay in a signal reaching different parts of the device.) In addition to advantageous location of the clock signal input pins for this purpose, the PLD also typically has clock signal distribution circuitry extending from each of these pins throughout the device in a way that helps to minimize skew.
There is increasing interest in adding high-speed serial interface (“HSSI”) circuitry to PLDs. HSSI circuitry typically employs various clock signals. It may therefore be desirable to provide ways to interface HSSI clock signal circuitry and other clock signal circuitry on a PLD.